Abstract
As semiconductor technology advances toward sub-2nm logic, high-bandwidth memory (HBM), and heterogeneous integration, lithography process control has become increasingly challenging. The rapid expansion of process complexity, together with the explosive growth of metrology, inspection, and equipment data, is creating unprecedented opportunities for Artificial Intelligence (AI) to transform how lithography processes are monitored, optimized, and controlled. The convergence of advanced analytics, machine learning, and domain-specific engineering knowledge is enabling a new generation of intelligent process control systems capable of delivering faster learning cycles, improved yield, and enhanced manufacturing productivity. This presentation explores the evolution from traditional rule-based lithography control toward AI-driven lithography process control. It discusses how modern semiconductor fabs can leverage large-scale process, metrology, and inspection data to improve overlay performance, critical dimension control, defectivity management, and scanner optimization. Particular attention is given to emerging AI applications, including virtual and augmented metrology, machine-learning-based context monitoring, process variation prediction, intelligent sampling strategies, and automated root-cause analysis. These capabilities enable engineers to identify hidden correlations, predict process excursions before yield impact occurs, and accelerate process optimization across development, ramp, and high-volume manufacturing environments. The talk further examines the integration of physics-based lithography knowledge with data-driven AI models. Rather than replacing engineering expertise, AI augments decision-making by combining semiconductor process understanding with advanced predictive analytics. This hybrid approach delivers more robust and explainable control solutions while maintaining the traceability and accountability required for manufacturing operations. Recent developments in AI-ready lithography platforms and engineering are also discussed, illustrating how agent-based workflows can transform lithography expertise into scalable, explainable, and user-validated process optimization frameworks. Finally, the presentation highlights future opportunities and challenges associated with deploying AI at scale in semiconductor manufacturing, including data governance, model reliability, explainability, and integration with existing advanced process control (APC) infrastructures. As the semiconductor industry enters the era of intelligent manufacturing, AI-driven lithography process control is expected to become a critical enabler for achieving the process capability, yield performance, and manufacturing agility required for next-generation technologies. Through practical examples and industry perspectives, this talk provides a vision of how AI will reshape lithography process control and accelerate the transition toward autonomous semiconductor manufacturing.
Biography
Dr. JinSeok Heo is a recognized expert in semiconductor patterning, lithography, and process control. With over two decades of industry experience, he has been instrumental in advancing EUV lithography adoption and semiconductor manufacturing innovation. At KLA, he works closely with leading semiconductor manufacturers to improve patterning performance, overlay control, and yield through advanced metrology, inspection, and data analytics solutions. Prior to KLA, he held senior technical leadership positions at Samsung Electronics R&D, leading EUV and immersion lithography programs. Dr. Heo received his Ph.D. in Mechanical Engineering from KAIST and has published more than 40 technical papers while securing over 20 patents in semiconductor technologies.
Abstract
Semiconductor complexity continues to increase with each new process node, as the industry pushes the limits of 2D scaling, 3D architectures, and advanced packaging to sustain ongoing performance improvements. EUV and High-NA EUV lithography, along with complex 3D device architectures such as Gate-All-Around (GAA) transistors and High-Bandwidth Memory (HBM) are introducing significant new challenges for process engineers. As a result, process control solutions must meet increasingly stringent requirements for sensitivity, precision, and image quality, often at sub-nanometer resolution. In this talk, I will review the key process control challenges arising from emerging architectures such as HBM and novel technologies like High-NA EUV, and discuss the solutions required to ensure effective control and high yield. I will present state-of-the-art eBeam approaches for both patterning and defect control including AI based solution in advanced semiconductor manufacturing and packaging, and highlight future directions for process control innovation.
Biography
Jason Kim (Sr. Director) has been managing TCT(R&D Extension) Korea organization within the Applied Materials PDC Business Group since 2020. After receiving BS in Electronic Engineering from Kookmin University, he began his career in the semiconductor industry at Samsung Electronics in 1998 and has approximately 30 years of experience in the field. He has experience working in Yield Enhancement Group and Metrology & Inspection Groups at Samsung Electronics, as well as CD-SEM Application Development at Hitachi High-Tech (Naka Factory) in Japan. At Applied Materials, he is responsible as the head of Korea R&D organization for driving System, Algorithm, and SW development across all metrology and inspection platforms.
Abstract
The introduction of extreme ultraviolet (EUV) lithography has enabled continued pitch scaling for advanced semiconductor devices. As the industry moves toward sub-2 nm logic technologies, however, patterning performance is increasingly limited by stochastic effects such as line-edge roughness (LER), line-width roughness (LWR), edge placement error (EPE), and other local variations. Although significant progress has been made in EUV exposure systems and photoresist materials, improvements in these stochastic variations have not kept pace with the scaling requirements of future technology nodes.
Considerable efforts are underway to develop next-generation photoresists, including metal-containing resists, to improve resolution and stochastic performance. However, resist innovation alone is unlikely to satisfy future patterning requirements. Additional improvements through post-lithography patterning processes are becoming increasingly important for reducing local variations while maintaining pattern fidelity.
This presentation will review the current status of advanced patterning technologies for sub-2 nm devices, focusing on the key challenges associated with continued scaling. The limitations of current patterning technologies, including LER/LWR, local CD variation, stochastic defects, and pattern fidelity, will be discussed together with potential approaches for their mitigation through process optimization and post-patterning techniques.
Special emphasis will be placed on the recent progress of Atomic Layer Etching (ALE), which has attracted significant attention as a promising technology for future semiconductor manufacturing. Owing to its atomic-scale process control and self-limiting reaction mechanism, ALE has the potential to improve pattern fidelity while minimizing process-induced damage. Recent developments in ALE, as well as the remaining technical challenges—including process integration, selectivity, productivity, and defect control—will be discussed.
Finally, perspectives on future advanced patterning technologies will be presented. As semiconductor manufacturing enters the era of atomic-scale process control, future progress will require close integration of lithography, plasma processing, materials, equipment, and process integration. The role of post-patterning technologies, particularly ALE, in overcoming the limitations of current EUV patterning and enabling future sub-2 nm device manufacturing will be discussed.
Biography
Dr. Bai received his Ph.D. in Plasma Physics from KAIST in 2002. Since joining Samsung Electronics the same year, he has been engaged in the development of advanced semiconductor technologies and currently serves as a Master (Vice President of Technology).
His expertise includes plasma etching, process monitoring, DRAM and logic process development, and EUV patterning. He has led the development of Samsung's EUV patterning, including the company’s first EUV multi-patterning technology and has contributed to both process and equipment innovations, including plasma etch systems and EUV mask defect mitigation. He has authored or co-authored nearly 100 technical papers and patents. His current research focuses on developing patterning for sub-2nm logic devices, including Atomic Layer Etching (ALE). He also serves on the program committees of SPIE Advanced Litho. + Patterning, DPS, and the ALD/ALE Conference.
Abstract
Optical projection lithography has remained central to the continuation of Moore’s Law for more than five decades. Since entering high-volume manufacturing in 2018, extreme ultraviolet lithography at 13.5 nm has enabled continued device scaling beyond the practical limits of 193 nm immersion lithography. Future extensions of EUV lithography are expected to rely on High-NA scanners and increasingly complex multipatterning approaches. Looking further ahead, continued numerical aperture scaling may face significant technical, manufacturing, and economic challenges. The Blue-X Technical Working Group, organized by EUV Litho, Inc., is investigating a complementary approach based on reducing the lithography wavelength below 13.5 nm while preserving the fundamental advantages of optical projection lithography. Blue-X is being explored as a possible path following High-NA EUV or, alternatively, as a strategic Plan B should Hyper-NA EUV prove less attractive from a technical or economic perspective. Rather than proposing an immediate replacement for EUV lithography, Blue-X seeks to determine whether wavelength reduction could provide another practical option for extending optical lithography into future technology generations. Since its launch in 2024, Blue-X has grown into an international collaboration involving semiconductor manufacturers, equipment and materials suppliers, universities, and national laboratories. Coordinated research is now underway in imaging and optical design, multilayer optics, photon sources, masks, metrology, and photoresists. Recent progress includes advances in multilayer mirror design, atomic spectroscopy and plasma modeling, resist and imaging analysis, and the initiation of experimental resist studies at 3.1 nm. This presentation will review the motivation for Blue-X, summarize recent progress across the Technical Working Groups, discuss the principal scientific and engineering challenges, and present an updated roadmap for evaluating the feasibility of advanced optical projection lithography at wavelengths below 13.5 nm.
Biography
Dr. Vivek Bakshi is Founder and President of EUV Litho, Inc., a consulting, education, and conference organization he established in 2007 to advance extreme ultraviolet lithography (EUVL). A globally recognized authority on EUV sources and next-generation lithography, he provides strategic and technical guidance to semiconductor manufacturers, suppliers, government agencies, national laboratories, universities, and investors. Since 2008, Dr. Bakshi has organized the annual International Workshop on EUV Lithography (EUVL Workshop) and the International Workshop on EUV and Soft X-ray Sources (Source Workshop), two internationally recognized conferences that have become leading forums for sharing advances in EUVL technology. Since 2025, the two workshops have been held together, along with annual short courses on EUVL and photon sources for lithography. He also teaches EUV short courses worldwide and presents at international conferences and industry events. Building on the success of EUV lithography in high-volume manufacturing, Dr. Bakshi is now leading the international Blue-X Technical Working Group, which is exploring optical projection lithography at wavelengths below 13.5 nm. Launched in 2024, the Blue-X TWG now includes more than 85 participating organizations from industry, universities, and national laboratories working collaboratively to evaluate the feasibility of lithography in the 2–7 nm wavelength region. He served for twelve years as an Associate Editor of JM³ (SPIE Journal of Micro/Nano Lithography, MEMS, and MOEMS) and is an Adjunct Professor in the School of Physics at University College Dublin. He has authored or co-authored more than 125 technical publications and five widely cited books on EUV lithography and holds three U.S. patents in the field. His latest book, Photon Sources for Lithography and Metrology (SPIE Press, 2023), reflects his continuing focus on next-generation photon source technologies. Today, his primary research interests include next-generation photon sources and the long-term roadmap for optical projection lithography below 13.5 nm.
Abstract
Driven by AI and HPC demands, High-NA EUV (NA 0.55) is critical for sub-1nm scaling, overcoming resolution limits despite challenges like stochasticity and stitching. Success requires holistic infrastructure readiness: curvilinear masks, CNT pellicles, advanced MOR/DRY resists, and precise OPC modeling. Industry leaders are aggressively deploying High-NA in memory and foundry roadmaps, leveraging collaborations with IMEC and LBNL for early validation. Furthermore, strengthening the supply chain via industry-academia partnerships is vital for indigenous innovation. This talk outlines a strategic vision for a resilient, localized ecosystem, ensuring sustainable technological leadership in the High-NA era through unified industry efforts.
Biography
ChangMin Park received the M.S. and Ph.D. degrees in electronic engineering from Korea University, Seoul, South Korea, in 2000 and 2010, respectively. In 2000, he joined the Process Development Team at the Semiconductor R&D Center, Samsung Electronics, where he has been engaged in the development of next-generation DRAM, FLASH, and Logic devices. His primary research interests include advanced photolithography processes, with a specific focus on Extreme Ultraviolet (EUV) lithography. He possesses over 16 years of specialized experience in EUV technology development.
Abstract
Extreme ultraviolet (EUV) lithography has become a core technology for leading-edge semiconductor manufacturing. Driven in part by the rapid expansion of artificial intelligence applications, the photoresist market, including EUV resists, is expected to grow substantially toward the 2030s. In recent years, the introduction of high-numerical-aperture EUV (High-NA EUV) exposure systems has enabled further improvements in resolution. At the same time, however, the requirements for thinner resist films and the suppression of pattern defects associated with higher-NA processing have become increasingly important challenges.
Market research reports predict growing demand for metal oxide resists as promising materials capable of meeting future high-resolution requirements. With the anticipated introduction of Hyper-NA EUV exposure systems, conventional chemically amplified resists are expected to face greater difficulties because of increasingly stringent film-thickness requirements, resolution limitations caused by acid diffusion, and the trade-off among sensitivity, resolution, and pattern roughness. The potential need for positive-tone metal-based resists for Hyper-NA EUV lithography has therefore been discussed.¹⁾ Accordingly, expectations for new resist materials and innovative material concepts are continuing to increase. It is anticipated that research and development conducted by academic institutions and other organizations will generate novel concepts and ideas that can ultimately lead to practical applications.
Meanwhile, global efforts toward a sustainable society and carbon neutrality are also expanding throughout the semiconductor industry. Lithographic processes consume large quantities of chemical materials, including photoresists and antireflective coatings. Research and development aimed at reducing or replacing per- and polyfluoroalkyl substances (PFAS) is therefore actively being pursued. Practical performance using fluorine-free materials in immersion ArF (iArF) lithography has already been reported.²⁾
From the perspective of carbon neutrality, EUV exposure systems consume substantially more electrical power than ArF lithography systems. As EUV lithography becomes more widely adopted and increasingly high exposure doses are required to achieve higher resolution, there is concern that energy consumption in semiconductor manufacturing processes will increase considerably. On the equipment side, research and development efforts are underway to achieve major improvements in energy efficiency by reducing the number of mirrors, developing higher-efficiency light sources, and designing new optical systems. However, a substantial improvement in resist sensitivity from the materials side could also make a significant contribution to reducing energy consumption and achieving carbon neutrality in semiconductor manufacturing.
In this presentation, we introduce our research and development activities toward low-dose EUV lithography. These activities include the development of metal-based resist materials using a process that combines EUV exposure with subsequent ultraviolet irradiation to reduce the required EUV exposure dose. We also present our planned activities for applying the developed materials to next-generation lithographic light sources.
Biography
Dr. Satoshi Enomoto received a M.S. in Industrial Chemistry from Nihon University in 2004. In 2004, he joined Toyo Gosei Co., Ltd. and began working on the development of chemically amplified resist materials. Subsequent research focused on materials for improving the viewing-angle performance of liquid crystal displays, the radiation-induced chemical reactions of photoacid generators, and the enhancement of chemically amplified resist sensitivity. In 2016, he began doctoral research at Osaka University on metal-containing chemically amplified resists utilizing polarity switching and crosslinking for EUV lithography. He received a Ph.D. in Engineering from the Graduate School of Engineering, Osaka University, in 2019 and currently serves as Director of the Photoresist Research Institute at Toyo Gosei Co., Ltd.
Abstract
Nanoimprint lithography, NIL, is now being explored for its potential as the alternative lithographic pathway to achieve carbon neutrality through sustainable semiconductor manufacturing due to its advantage of power consumption to EUV lithography, EUVL. Since there is no limitation in size of resist formation once the template is fabricated, technology for scaling down of templates is quite significant for state-of-the-art semiconductor device fabrication.
For years, we have been working on the resolution improvement of E-beam written master template and its replication process by NIL simultaneously. Due to the replication technology, the impact of adopting cost and time-consuming processes for master fabrication such as low-sensitivity resist, small beam size MBMW, and even multiple patterning is significantly reduced. Based on general technology roadmaps for logic devices, metal pitch scaling continues and below pitch 20nm is required in the Angstrom era.
For catching up the device scaling, not only the improvement of EB lithography performance but also the introduction of alternative patterning technology such as self-aligned double patterning, SADP need to be considered. Recently, the ALD tool for template manufacturing was installed and hp10nm L/S patterning results by using SADP was presented. In this presentation, we report on the work to achieve below hp10nm resolution including the optimization of EB lithography for core patterning. Additionally, the demonstration of cutting process applying to patterns generated by SADP is presented.
This work was previously presented at SPIE Advanced Lithography + Patterning 2026
Proc. SPIE Volume PC13982, Novel Patterning 2026; PC139820B
Biography
Takaharu Nagai joined Dai Nippon Printing in 2006, after receiving a master's degree in mechano-informatics from University of Tokyo. For the first 3 years, he worked for ArF mask and lithographic technology development. Since the beginning of NIL project in 2009, he has been engaged in the development of template replication technology and, more recently, EB writing pattern generation by using MBMW.
Abstract
Recent advances in information technology, particularly generative artificial intelligence, have accelerated the demand for further semiconductor scaling. In EUV lithography, high-numerical-aperture (high-NA) exposure systems are being introduced, while hyper-NA exposure is also under discussion. Because increasing the NA reduces the depth of focus (DoF), mitigating mask three-dimensional (M3D) effects is becoming increasingly important. High-k absorbers with strong EUV absorption are promising materials for reducing M3D effects. For practical application, however, they must provide chemical stability against mask cleaning processes and hydrogen-containing exposure environments, as well as sufficient dry-etching capability for precise patterning. In this study, CuX and NiZ films were developed as novel high-k absorbers for high-NA and hyper-NA EUV lithography. Durability tests simulating mask cleaning and exposure environments showed only minor changes in film properties. Tailored etching processes also provided favorable etching performance and high selectivity to the hard-mask material. Although further optimization of the etched profiles is required, the results demonstrate promising patterning feasibility. Lithographic simulations further showed wider process windows than conventional absorbers and recently proposed low-n, high-k materials. These results indicate that CuX and NiZ are promising EUV mask absorbers for future high-NA and hyper-NA lithography.
Biography
Received a master’s degree in Chemical System Engineering from the Graduate School of Engineering, The University of Tokyo in 2018. Joined AGC Inc. in 2018 and has been engaged in materials development for EUV mask blanks.
Abstract
The growing demand for advanced logic semiconductors in post-5G and next-generation information and communication systems is increasing the need for high-power extreme ultraviolet (EUV) lithography. Consequently, pellicle membranes with high thermal stability and durability under intense EUV irradiation are required. Carbon nanotube (CNT)-based pellicles are promising candidates owing to their excellent thermal stability and high EUV transmittance. Our objective is to develop CNT pellicles exhibiting EUV transmittance above 95% while withstanding 1000 W-class EUV light sources.
To satisfy these requirements, CNT pellicles require high thermal resistance and hydrogen plasma durability. These properties can be achieved through precise control of CNT characteristics and optimization of the CNT bundle nonwoven structure for enhanced mechanical stability and reduced plasma exposure.
CNT purification processes were investigated to reduce residual iron catalyst originating from CNT synthesis and improve thermal stability, as evaluated by thermogravimetric (TG) analysis. Free-standing CNT membranes were fabricated by a wet-process method and characterized using an original scanning electron microscopy (SEM) image-analysis technique. The effects of CNT properties and membrane microstructures on hydrogen plasma durability are discussed.
Biography
Isao Ichikawa received his M.S. degree in Chemistry from Tokyo Institute of Technology (currently Institute of Science Tokyo), Japan, in 1996 and his Ph.D. degree in Materials Science from the same university in 2015. He worked for Toshiba Chemical Corporation (now Kyocera Corporation) from 1996 to 2005. Since joining LINTEC Corporation in 2005, he has been involved in the research and development of materials for semiconductor packaging applications. Since 2022, he has focused on the development of advanced materials and components for semiconductor front-end processes.
Abstract
As EUV lithography advances beyond the 2 nm technology node, EUV mask inspection requires higher defect detection sensitivity and stable inspection performance. While e-beam and actinic inspection provide high sensitivity, their application in high-volume manufacturing remains challenging due to tool cost and cost of ownership. DUV inspection is therefore attracting attention as a practical alternative for EUV mask manufacturing. In this study, programmed defect masks based on 2nm, 1xnm logics and advanced DRAM patterns were evaluated to improve DUV inspection performance. Defect signal analysis revealed a strong dependence on base pattern dimensions and pattern contrast, with reduced sensitivity observed for specific pattern size ranges. To address this limitation, we investigated inspection optimization through both focus offset and light calibration control. Pattern contrast analysis showed that these optical parameters influence defect visibility, with focus offset providing the strongest impact on contrast modulation and defect signal enhancement. Using optimized inspection conditions derived from focus offset and light calibration evaluations, sensitivity gaps observed under conventional settings were eliminated, and all target programmed defects became detectable. Furthermore, the proposed method was applied to phase-shift masks and Ta-based curvilinear patterns, where improved defect detectability and target sensitivity were also achieved. These results demonstrate that optimization of optical inspection conditions, including focus offset and light calibration, significantly enhances DUV inspection performance and supports the applicability of DUV inspection tools to EUV masks beyond the 2 nm node, contributing to accelerating EUV mask development cycles and stable HVM.
Biography
Norifumi Hosoi joined Tekscend Photomask in 2025, where he has been engaged in photomask inspection and related process technologies. His work focuses on the development, optimization, and application of inspection methodologies for advanced semiconductor photomasks, contributing to quality assurance and process improvement in semiconductor manufacturing. His research interests include mask inspection, wafer simulation, and metrology technologies for next-generation semiconductor devices.
Abstract
Compared with mature DUV photomask fabrication, EUV mask manufacturing employs many of the same core process tools, including resist coaters/developers, mask writers, etchers, CD-SEMs, and cleaning systems. The technologies that fundamentally distinguish EUV masks are the Mo/Si multilayer (ML) blank, actinic inspection, and the pellicle. Consequently, the most significant challenge and infrastructure investments in EUV mask defect control have centered on these three unique areas. This presentation will review inspection solutions developed for each of these technologies and discuss their extension to high-NA EUV masks.
Inspection has played an indispensable role throughout the development of EUV mask technology and has become even more critical for high-volume manufacturing. As the saying goes, “If you can’t measure it, you can’t improve it.” Inspection is the most frequently utilized step than any others in the mask process and usage flows. In particular, actinic blank inspection (ABI) and actinic patterned mask inspection (APMI) have emerged as essential technologies, enabling not only defect-free mask fabrication but also effective reticle monitoring and defect control in wafer manufacturing.
This presentation will first provide an overview of the inspection methodologies employed throughout the entire EUV mask lifecycle, from multilayer blank fabrication at blank suppliers and mask manufacturing in mask shops to reticle monitoring and requalification in wafer fabs. I will present analysis and representative examples that demonstrate the capabilities of actinic inspection for both multilayer blanks and patterned masks, as well as inspection technologies for EUV pellicles. The presentation will highlight the generations of APMI platform ACTIS that meet the defect control requirements for both 0.33NA and 0.55NA EUV masks and the roadmap for continued advancement in inspection sensitivity and speed.
Biography
Dr. Ted Liang is Senior Director of Engineering at Lasertec USA, where he continues to pursue his passion for technological innovation in EUV mask inspection solutions. Ted joined Lasertec in 2025 following his retirement from Intel Corporation after 29 years. He has played an instrumental role in developing EUV mask infrastructure and influencing the industry’s adoption of key mask technologies. His major contributions to the mask industry include e-beam mask repair, the invention of the Ru-cap for Mo-Si multilayer blanks that has been used industry-wide, actinic blank inspection, EUV AIMS, actinic patterned mask inspection, and EUV pellicles. Ted received two Intel Achievement Award for his technical accomplishments.
A recognized leader in the lithography and photomask community, Dr. Liang is a SPIE Fellow, holds six patents, and has over 60 publications. He frequently supports the technical community by serving on program committees and as a conference chair. Demonstrating his sharing of knowledge, his four-hour course, “EUV Mask Inspection and Repair: Technology and Practice,” attracted the highest attendance at the 2026 SPIE Lithography Conference.
Dr. Liang holds a Ph.D. in Materials Science and Engineering from the University of Wisconsin–Madison.
Abstract
The demands placed on EUV lithography continue to grow faster than current EUV sources can meet them. In this presentation, I will discuss the case for an industrial scale EUV Free Electron Laser (FEL) as the light source for advanced semiconductor manufacturing, covering what changes for the patterning process, for the fab, and for the longer-term roadmap. I will highlight the source characteristics that matter most to EUV lithography: substantially higher dose, a polarized output that improves image contrast, and a wavelength that is selected rather than fixed.
Biography
Brandon Holybee is a Senior Lithography Applications Scientist at xLight Inc., where he leads the lithography experiments and computational work demonstrating the advantages of FEL driven EUV lithography over conventional laser produced plasma sources. He brings over seven years of experience in EUV lithography, advanced materials characterization, and advanced device integration. Previously, in Intel’s Technology Research division, he contributed to the development of advanced lithography capabilities spanning low-NA and high-NA EUV and e-beam process development, EUV resist and materials research, and integration for emerging semiconductor devices. His work focuses on process innovation, characterization methods, and next-generation patterning technologies that support the future of semiconductor manufacturing.
Abstract
Forty years after it was first proposed in 1986, extreme ultraviolet (EUV) lithography has evolved from a research concept into the cornerstone of advanced semiconductor manufacturing. Today, ASML’s 0.33 NA EUV systems are widely used in high-volume manufacturing, enabling the production of leading-edge logic and memory devices. Continuous improvements in source power, overlay performance, and system productivity have made EUV a mature and cost-effective technology. The industry is now transitioning to High-NA EUV (0.55 NA), with multiple EXE:5000 and EXE:5200B systems already installed and qualified. Recent innovations, including 1 µm pre-pulse source technology and wafer stocker integration, have increased throughput to 175 wafers per hour, bringing High-NA closer to high-volume manufacturing. Looking further ahead, Hyper-NA EUV (~0.75 NA) is emerging as a promising path for continued scaling. By leveraging the existing EUV infrastructure and mask ecosystem, Hyper-NA could provide higher resolution, improved image contrast, and lower pattern variability, supporting future device architectures such as CFET and dense 2D interconnects. Together, the roadmap from 0.33 NA EUV to High-NA and future Hyper-NA technologies highlights EUV’s central role in extending semiconductor scaling. Through ongoing innovation in optics, light sources, and patterning technologies, EUV is expected to remain the foundation of advanced semiconductor manufacturing in the AI era.
Biography
Sungmin Huh is a Field Marketing Manager at ASML Korea, where he leads strategic initiatives in advanced lithography and patterning technologies. Prior to joining ASML, he served for 20 years as a Principal Engineer at Samsung Electronics’ R&D Center, conducting research and supporting high-volume manufacturing (HVM) activities for EUV masks and lithography. From 2008 to 2010, he also served as a project leader at SEMATECH, where he focused on EUV mask infrastructure. He was also a member of the BACUS Steering Committee.
Abstract
The transition from deep ultraviolet (DUV) to extreme ultraviolet (EUV) lithography has been a key enabler of continued DRAM scaling, supporting 10 nm-class technologies through improved patterning capability and reduced process complexity. However, the scaling limitations of conventional 6F² architectures, together with rapidly growing demand for high-density and high-bandwidth memory driven by AI-centric computing, are motivating the exploration of alternative technology pathways.
Recent advances in lithography, patterning integration, and computational methodologies continue to extend the capabilities of EUV, while High-NA EUV is expected to provide an additional scaling path for future memory generations. At the same time, emerging approaches such as DSA-assisted patterning, 4F² cell concepts, and 3D DRAM architectures are attracting increasing attention across the industry.
This presentation reviews the evolution of DRAM patterning from DUV to EUV and discusses future technology directions beyond conventional 10 nm-class scaling. A broad industry perspective is provided on how advanced lithography and emerging memory architectures may support future memory requirements in the AI era.
Biography
Jeonghoon Lee is a Principal Member of the Technical Staff in the Anstrom Patterning Team at imec. He received his Master’s degree in Metallurgical Engineering from Hanyang University in 1999. In August 1999, he began his career as a lithography engineer at Samsung Electronics, where he was later promoted to Principal Engineer with Patterning Strategy staff and served as a Module leader of Logic OPC/Project Leader of VNAND OPC part in the Process Development Team of the Device Solutions (DS) Division until February 2020. In March 2020, he joined imec, where he is currently working on several patterning projects as a Principal Member of the Technical Staff.
Abstract
This talk presents actinic EUV/Blue-X characterization of advanced materials for semiconductor and lithography applications. These capabilities enable a wide range of actinic EUV/Blue-X characterization studies for semiconductor materials. We conduct such studies on EUV/Blue-X-related materials such as photoresists, pellicles, and masks using actinic EUV/Blue-X light sources, including synchrotron radiation and high-harmonic generation (HHG) light sources. In this presentation, we introduce our recent studies on carbon nanotube (CNT) pellicles and silicon oxide photoresists using EUV and Blue-X beams. We evaluate the transmission, reflection, scattering, and thermal stability of CNT pellicles. Furthermore, we discuss latent images with 10 nm resolution and infrared spectra of silicon oxide photoresists.
Acknowledgments. This work was supported by National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (NRF-RS-2024-00443105, NRF-2022M3H4A308806913)
[1] SPIE ALP 2026, Paper 13979-65 (to be published)
[2] SPIE ALP 2026, Paper 13981-109 (to be published)
[3] SPIE ALP 2026, Paper 13981-126
Biography
Jiho Kim is a staff scientist for the EUV beamline in Pohang Accelerator Laboratory (PAL). He earned his Ph.D. in Physics from the University of Seoul (UOS) and completed postdoctoral research at the 12D IRS and PAL-EUV beamline in PAL. Currently, he is designing the EUV beamline facilities. Also, he is focusing on testing and evaluating materials and devices for extreme ultraviolet lithography (EUVL), including EUV photoresists, masks, and pellicles.
Abstract
As the semiconductor industry pursues higher memory density and performance, 3D DRAM introduces new process and metrology challenges driven by increasingly complex high-aspect-ratio structures, buried features, and tight process windows. This talk will discuss key 3D DRAM process challenges and the critical role of shape metrology solutions in accelerating technology development. Critical-dimension small-angle X-ray scattering (CD-SAXS) technology combines non-destructive, high-resolution 3D profile metrology with unique sensitivity to buried and high-aspect-ratio structures. We will explore how KLA's Axion® CD-SAXS technology enables measurement of critical 3D DRAM parameters such as deep trench profiles and lateral recesses, providing insights difficult to obtain with conventional approaches. Application examples will demonstrate how Axion supports process optimization and successful realization of 3D DRAM.
Biography
Dr. Tianhan Wang Played a key role in the first production-ready implementation of small-angle X-ray scattering (SAXS) for semiconductor metrology, leading development and deployment of all Axion products including T1000, T2000, and T2500. Prior experience spans applications engineering for Optical CD and Film products. Currently serves as Axion Product Line Manager, driving product strategy and execution. Tianhan earned his Ph.D. in Materials Science and Engineering from Stanford University.
Abstract
As the industry moves toward 3D architectures and advanced packaging, X-ray techniques are becoming increasingly important for the inspection of buried defects and the metrology of layered structures. This talk will review the state of the art in X-ray technologies, spanning high resolution x-ray imaging, materials characterization approaches, and fault isolation. This talk will provide educational background to understand key system differentiation while also acknowledging key limitations to existing approaches in comparison to the synchrotron. Finally, we will conclude each x-ray technique section with an overview of existing and potential applications, including new developments in the broader x-ray community.
Biography
Sylvia Lewis co-founded Sigray, a leader in advanced x-ray technologies. After Sigray’s acquisition by Applied Materials, Ms. Lewis became the General Manager of the newly formed Applied XCT business unit. Ms. Lewis has over 15 years’ experience in high resolution x-ray imaging at Zeiss X-ray Microscopy and Sigray. She received a Bachelor’s degree in Electrical Engineering at Stanford University, and received a Masters Degree in Physics from Johns Hopkins.
Abstract
The rapid expansion of AI and high-performance computing has accelerated the adoption of advanced packaging technologies, including HBM, 3D IC, Co-Packaged Optics (CPO), and panel-level packaging. As device architectures and manufacturing processes become increasingly diverse, metrology and inspection (MI) face new challenges that extend beyond conventional process control. Addressing these challenges requires not only product-specific solutions but also common technology foundations that can be leveraged across multiple advanced packaging platforms. This presentation provides an overview of major advanced packaging technologies and discusses the corresponding MI requirements and technical challenges associated with HBM, 3D IC, CPO, and Panel applications. Key MI topics—including overlay, surface topography, warpage, and defect inspection—are examined to highlight both the unique requirements of each product and the common technical issues shared across different packaging platforms. Finally, the presentation discusses common MI technology directions that can support multiple advanced packaging applications, emphasizing opportunities to transfer knowledge and technical capabilities across product domains. The evolving role of metrology and inspection in enabling robust manufacturing and future advanced packaging technologies will also be presented.
Biography
Byeongkyu Cha is the Advanced Packaging Metrology and Inspection (MI) Group Leader at the Semiconductor R&D Center of Samsung Electronics. He leads the development of metrology and inspection technologies for a wide range of advanced packaging applications, including 3D stacking and 2.xD heterogeneous integration. He received his B.S. and M.S. degrees in Mechanical Engineering from Hanyang University and has more than 20 years of experience in semiconductor process and equipment development.
Abstract
Recently, electron microscopy has undergone a transformative leap by developing multislice electron ptychography (MEP) that set a new record resolution of 23 pm, approaching the limit set by phonon vibrations. This technique not only allows ultra-high resolution, but is also capable of reconstructing three-dimensional atomic structures from a single scan. MEP performs quantitative phase reconstruction at the atomic scale, achieving picometer resolution in the lateral plane and nanometer-scale depth resolution in the axial direction. Therefore, MEP allows us to visualize the detailed defect structures within crystals without the need for tilting or obtaining multiple projections, overcoming the limitations of the conventional projection-based S/TEM imaging.
Here, we demonstrate atomic-scale three-dimensional reconstruction of freestanding oxide membranes using electron ptychography. By exploiting the multislice algorithm and superior resolution of ptychographic imaging, we reconstruct the 3D atomic structure of freestanding BaTiO₃ membranes and directly visualize structural defects that are obscured in projection-based imaging. The method further enables volumetric characterization of membrane–membrane interfaces in stacked freestanding heterostructures, revealing the local atomic arrangement across bonding regions. Our approach transforms electron ptychography into a platform for three-dimensional atomic metrology for direct investigation of defects, interfaces and lattice distortions that highly affect the performance of various devices.
Biography
Prof. Celesta S. Chang is currently an assistant professor in Dept. of Physics and Astronomy at Seoul National University, Korea.
She earned her bachelors from Department of Physics at Yonsei University, Korea in 2014, masters and Ph.D. from the Department of Physics at Cornell University, USA in August 2020. She worked as a postdoctoral associate in the School of Applied and Engineering Physics at Cornell University for 6 months, and another 2.5years in Research Laboratory of Electronics at MIT. She joined Seoul National University as a faculty in August, 2023.
During her Ph.D., her work was focused on understanding various oxide and nitride materials as well as device heterostructures by transmission electron microscopy (TEM). She was nominated as a National Science Foundation (NSF) fellow in 2015-2020. At MIT, she extended her expertise by developing remote epitaxy of oxides. Now at SNU, she utilizes PLD for oxide film growth and is focusing on observing oxides with TEM.
Abstract
As semiconductor packaging technologies continue to evolve toward higher integration densities, wafer-to-wafer (W2W) bonding has emerged as a key enabling process for advanced three-dimensional (3D) integration, heterogeneous integration, and hybrid bonding applications. The success of W2W bonding strongly depends on the surface topography and edge geometry of the wafers being bonded. Among various geometric parameters, wafer edge roll-off (ERO), defined as the gradual deviation of wafer surface height near the wafer edge, has become an increasingly critical factor affecting bonding yield, overlay accuracy, wafer handling stability, and post-bonding reliability. Excessive edge roll-off may induce localized gaps, non-uniform bonding pressure distribution, void formation, and edge-related defects, ultimately reducing manufacturing yield and device performance. Consequently, accurate characterization of ERO at nanometer-scale resolution has become an essential metrology requirement for high-volume semiconductor manufacturing. Various metrology techniques have been investigated for ERO measurement. Atomic Force Microscopy (AFM) is widely recognized for its exceptional vertical resolution at the nanometer and sub-nanometer scale. AFM enables detailed characterization of local surface morphology and provides highly accurate topographic information. However, its practical application to ERO inspection in production environments is limited by its relatively small field of view, slow scanning speed, and difficulty in measuring long edge profiles over several millimeters. As semiconductor manufacturing increasingly demands full-wafer and high-throughput inspection capabilities, AFM is primarily utilized for reference measurements and localized verification rather than inline process monitoring. Optical triangulation techniques represent another widely adopted approach for measuring wafer edge geometry. These methods offer non-contact operation, relatively simple system architectures, and fast acquisition speeds. Optical triangulation can efficiently measure large-scale geometric profiles and is often used for wafer edge inspection and dimensional metrology. Nevertheless, its measurement accuracy is fundamentally constrained by spot size, sensor resolution, and triangulation geometry. Furthermore, measurement uncertainty tends to increase when inspecting highly reflective semiconductor surfaces or when nanometer-level height precision is required. These limitations restrict the applicability of optical triangulation for advanced hybrid bonding processes where extremely tight topography specifications must be satisfied. Interferometric metrology has emerged as a promising solution for overcoming the limitations of existing measurement techniques. By exploiting optical phase information, interferometric systems provide nanometer-scale vertical resolution while maintaining a relatively large measurement field and high acquisition efficiency. Various interferometric approaches, including phase-shifting interferometry (PSI), white-light interferometry (WLI), and coherence scanning interferometry (CSI), have demonstrated excellent capability in measuring ultra-flat semiconductor surfaces. However, the measurement of wafer edge roll-off presents unique challenges due to steep local slopes, large measurement ranges, and the requirement for high-speed operation compatible with massproduction environments. In this study, a high-precision and high-speed interferometric metrology system was developed specifically for quantitative ERO characterization in wafer-to-wafer bonding applications. The proposed system combines advanced interferometric measurement principles with optimized optical design and dedicated signal processing algorithms to achieve accurate edge profile reconstruction over extended measurement regions. Unlike conventional interferometric systems that are often optimized for central wafer inspection, the developed architecture was designed to maintain measurement fidelity in the wafer edge region where topographic gradients become increasingly significant. The developed methodology enables nanometer-scale vertical measurement precision while covering the entire ERO region within a single measurement sequence. Through optimized acquisition strategies and high-speed image processing, the system significantly reduces measurement time compared with traditional scanning-based methods. Experimental evaluations were performed using semiconductor wafers representative of advanced packaging processes. The measurement results demonstrated excellent repeatability, reproducibility, and correlation with reference metrology methods. The proposed interferometric approach successfully captured subtle edge profile variations that are difficult to resolve using conventional optical triangulation systems while achieving substantially higher throughput than AFM-based measurements. Furthermore, the obtained ERO profiles provided valuable quantitative information for process optimization and quality control in wafer bonding production lines. The ability to rapidly characterize edge topography enables early detection of process-induced variations, supports wafer quality classification, and contributes to improved bonding yield prediction. The measurement data can also serve as an important input for process modeling and predictive manufacturing frameworks aimed at reducing defect formation during bonding operations. In conclusion, accurate ERO characterization is becoming increasingly important as wafer-to-wafer bonding technologies advance toward tighter process tolerances and higher manufacturing volumes. While AFM and optical triangulation each offer unique advantages, their limitations in throughput, measurement range, or precision restrict their effectiveness for high-volume production environments. The interferometric metrology system presented in this work demonstrates that high-speed and high-precision ERO measurement can be simultaneously achieved through optimized interferometric design. The proposed approach provides nanometer-scale measurement capability, large-area coverage, and productioncompatible throughput, making it a highly promising solution for next-generation semiconductor bonding processes. The developed technology is expected to contribute significantly to process control, yield enhancement, and reliability improvement in advanced semiconductor manufacturing
Biography
Joonho You is currently the CEO of Nexensor Inc. He studied optical metrology at KAIST (Korea Advanced Institute of Science and Technology) and has over 20 years of experience in research, development, and commercialization in this field. His research interests include interferometric technologies, thin-film measurement technology, shape measurement techniques using pattern projection methods such as deflectometry and Moiré, and property analysis with femtosecond laser. He is the member of The Korean Microelectronics and Package Society , Korean Optical Society of Korea.
Abstract
Feature-scale ion transport is expected to become a key challenge for next-generation high-aspect-ratio contact (HARC) SiO₂ etching as feature aspect ratios continue to increase. This work investigates the feasibility of ultra-low-pressure inductively coupled plasma (ICP, < 5 mTorr) as a transport-oriented process platform for future HARC etching. The effects of process pressure, source power, bias power, and gas chemistry were systematically investigated using HARC SiO₂ patterns.
Ultra-low-pressure operation significantly improved profile integrity by reducing entrance distortion (ΔCDtop) and aspect-ratio-dependent etching (ARDE), indicating enhanced directional ion transport into high-aspect-ratio features. Process pressure was identified as the primary factor governing feature-scale ion transport, while source power, bias power, and gas chemistry independently controlled ion flux, ion energy, and etch selectivity, respectively.
These results demonstrate that ultra-low-pressure ICP provides the transport foundation required for the independent optimization of plasma characteristics. It therefore represents a promising process platform for future transport-limited HARC technologies.
Biography
Abstract
As semiconductor device scaling continues to advance, EUV lithography has become a key technology for high-resolution patterning. However, stochastic effects and pattern profile variations generated during the lithography process can lead to critical dimension (CD) variation, line-edge roughness (LER), and poor pattern fidelity. Since hard mask patterns serve as the primary template for subsequent pattern transfer processes, precise control of pattern geometry is essential for achieving robust process margins and high device yield.
This session will present an overview of Ion Beam Etching (IBE) for pattern shaping
applications, including the underlying shaping mechanisms and the key process
parameters governing pattern profile control.
Biography
Abstract
The critical dimensions of semiconductor devices are continuously shrinking, reaching the nanometer and even angstrom scale in both 2D and 3D structures. As a result, the demand for atomic-scale precision in etching processes is rapidly increasing. This talk will present various plasma-enhanced atomic layer etching (PEALE) processes developed for both anisotropic and isotropic patterning of metals and dielectric materials, including molybdenum, ruthenium, cobalt, titanium nitride, tantalum nitride, aluminum oxide, hafnium oxide, zirconium oxide, silicon oxide, and silicon nitride. Typical atomic layer etching (ALE) processes consist of two sequential steps: surface modification and material removal. Various surface modification techniques have been employed, including fluorocarbon film deposition, surface fluorination, chlorination, and oxidation using plasma-generated radicals. In the subsequent removal step, the modified layers are eliminated through methods such as ion bombardment, thermal desorption, ligand exchange, ligand volatilization, or halogenation. This talk will also cover key characteristics of plasma-enhanced ALE processes, including reaction kinetics, selectivity, surface roughness, and residual surface contamination.
Biography
Heeyeop Chae is a Professor in the School of Chemical Engineering at Sungkyunkwan University (SKKU), Korea. He received his Ph.D. in plasma chemical kinetics and surface reactions from Massachusetts Institute of Technology. His research focuses on the plasma-enhanced atomic layer etching, low global warming etch gases, and plasma monitoring using machine learning techniques. His email address is hchae@skku.edu.
Abstract
Back‑end‑of‑line (BEOL) metal layers with a 2× pitch are still patterned using ArF immersion lithography regardless of the technology generation. While 1× metal layers have already been shrunk from 3x nm and 1x nm pitches, the existing EUV printing budget is already saturated, making a transition of 2× metal layers to EUV infeasible from a cost perspective for foundries. Nonetheless, as process nodes continue to scale down, the required shrink for 2× metal layers has progressed from 80 nm to 76 nm and below, and for products developed under optical‑shrink constraints the pitch approaches the limit of ArF capability. In this paper we propose a series of methods to maximize the margin for 2× metal pitch shrink while retaining ArF immersion lithography: TDLO‑based selective pitch release – a targeted double‑patterning approach that locally relaxes pitch constraints without adding extra masks. Defectivity model for OPC optimization – a physics‑based model that predicts layout‑dependent printing defects, enabling robust optical proximity correction (OPC) tuned for the aggressive pitch. Target‑Optimization Inverse Lithography Technology (T‑ILT) – an inverse‑lithography framework that jointly optimizes mask patterns and process targets to achieve the desired critical dimensions with minimal overhead. By integrating these techniques, we demonstrate a feasible pathway for next‑generation BEOL patterning that preserves the economic advantages of ArF immersion lithography while meeting the ever‑tightening pitch requirements of future semiconductor nodes.
Biography
Abstract
Siemens EDA fully recognizes the importance of processing and analyzing the massive volumes of metrology data being generated in today’s semiconductor industry. We aim to achieve more than 3X reduction of the flow by identifying the reasons why the processing and analysis of large-scale metrology data is not being carried out effectively and proposing the solutions in three key areas. The first is the ability to support a wide range of use cases and second is the quantitative KPIs required for quality analysis at each step of data handling. Third is the time required to develop a processing and analysis solution—that is, the time taken to create and execute recipes.
Calibre AMM automates the entire process for CD matching between SEM images generated by various SEM-based metrology systems such as Hitachi SEM, EP5, and NGR, and quantifies each step using KPIs. When performing contour pre-filtering for the use with OPC, contour extraction using AMM outputs detection scores as a contour confidence indicator. We demonstrated data cleaning on over 20,000 Hitachi SEM contours, successfully performing approximately 10% filtering within three days. GPU-accelerated and AI-compatible AMM engine also around the corner.
As a differentiation of Siemens technology, Siemens continues enhancing the metrology capability in advanced tech nodes.
Biography
'I have been working in the area of photolithographic process development and RET/OPC (optical proximity correction) since January, 1997. Most of my career has been focused on RET/OPC and mask quality control after six years of my service as process and OPC development engineer in SK hynix.
I’m proud that I was a member of the first OPC team in SK hynix R&D where initially OPC was manually optimizing DRAM cell/periphery by utilizing aerial image based simulator followed by automated fullchip OPC setup at 0.13nm technology node. Then I moved to SEA area working in Silterra Malaysia, Chartered Semiconductor, and X-FAB Malaysia for 10 years where I was fully dedicated to RET/OPC and mask quality control.
In 2012, I had the opportunity to join Siemens EDA (formerly known as Mentor Graphics). I started in the role of OPC AE and transitioned to technical sales role in 2015, where I have been responsible for developing Calibre product portfolio and promoting it to Korea customers.
Abstract
Curvilinear optical proximity correction (OPC) treats segments as curves rather than lines and offers improved correction accuracy. In standard OPC flows, however, once a set of segments is identified through fragmentation, it remains the same throughout OPC iterations, which limits OPC performance in both runtime and accuracy. In this talk, we present an additional step of re-fragmentation that can be integrated with curve correction inside the OPC iteration loop. Two machine learning (ML) models are applied for quick re-fragmentation: U-Net is used to detect critical segments, and MLP identifies the point along the critical curve where the curve should be divided. The reference samples used to train the MLP are generated through Bayesian optimization.Compared to standard OPC, the proposed method yields a substantial reduction in OPC iterations (from 20 to 15) and runtime (from 188 s to 152 s), on average across test clips, when a target vertex placement error (VPE) is given. If the number of OPC iterations is fixed to 25, the proposed method yields an average VPE of 1.12 nm, much smaller than the 1.65 nm achievable through standard OPC.
Biography
Seohyun Kim is a Ph.D. student in the School of Electrical Engineering at KAIST, where she also received her B.S. and M.S. degrees. She is advised by Prof. Youngsoo Shin, and her research lies in computational lithography and design-technology co-optimization (DTCO), with a particular focus on curvilinear optical proximity correction (OPC) and machine learning-based mask optimization.
She is the first author of multiple peer-reviewed papers on ML-guided curvilinear OPC, including techniques for re-fragmentation, curve correction, and critical segment classification. She also works on the synthesis of critical mask patterns to enhance lithography simulation. Her recent work has been published in IEEE Transactions on Semiconductor Manufacturing and SPIE Advanced Lithography, and was recognized with the ISE President Best Paper Award at ISOCC 2024. Her research aims to enable fast, accurate, and manufacturable OPC through the integration of machine learning-based optimization.
Abstract
Traditional nanofabrication techniques often rely on toxic chemicals and harsh processing conditions that are incompatible with delicate biological materials. To overcome this, recent advancements have established natural and genetically engineered proteins, specifically silk fibroin, as versatile, eco-friendly resists for next-generation lithography, including both electron-beam lithography (EBL) and deep-ultraviolet (DUV) photolithography. By exploiting irradiation-induced polymorphic transitions—where targeted exposure modulates the protein's secondary structures between water-soluble amorphous coils and water-insoluble β-sheets or α-helices—researchers have achieved entirely water-based, high-resolution nanoscale patterning. These protein resists exhibit exceptional characteristics, including sub-50 nm resolution capability, highly selective dry-etching resistance, and inherent biocompatibility that preserves the activity of embedded functional dopants like enzymes or fluorophores. Consequently, this green lithographic paradigm enables the direct monolithic integration of biological matrices with metallic and nanophotonic structures. Demonstrated applications range from wavelength-scale, ultra-high-resolution (80k DPI) structural color filter arrays and Fabry-Pérot resonators to bio-integrated electronic sensors and 2.5D encrypted security patches. Ultimately, protein-based lithography provides a robust and sustainable platform bridging the gap between high-performance nanofabrication and next-generation biomedical devices.
Biography
Dr. Sunghwan Kim is currently a Professor in the Department of Biomedical Engineering and the Department of Electronic Engineering (Graduate) at Hanyang University. He received his B.S. and Ph.D. degrees in Physics from Seoul National University in 2004 and 2010, respectively.
Following his doctoral studies, Dr. Kim worked as a postdoctoral researcher at Seoul National University and in the Department of Biomedical Engineering at Tufts University. Before joining Hanyang University in 2022, he served as an Assistant, Associate, and Full Professor in the Department of Physics at Ajou University from 2013 to 2022.
Dr. Kim has been actively contributing to the field of lithography and optics. He currently serves as a Committee Member for the Next Generation Lithography (NGL) Conference and as the Secretary of the Lithography Division in the Optical Society of Korea. In recognition of his outstanding research and contributions to the field, he was honored with the ASML Young Investigator Award in 2017 and the ASML TechTalk Young Professor Award in 2018.
Abstract
We introduce next-generation digital lithography (Laser Direct Imaging, LDI) technology, which demonstrates significant application potential in the fields of PCB and semiconductor packaging. By leveraging maskless direct imaging, it offers superior fine-pattern capability, unmatched process flexibility, and significant cost saving compared to conventional exposure technologies.
Our scalable product lineup ranges from cost-effective R&D systems to high-precision, high-throughput platforms for volume manufacturing. This ensures seamless transfer of recipes and know-how from development to production, accelerating your technology roadmap.
Biography
Philip Kim is a Research Fellow and Task Leader at the LG Production engineering Research Institute. In July 1996, he began his career as a Chief Research Engineer at Samsung Electronics, where he served until October 2003. In November 2003, he joined Philips (Philips Optical Storage) as a Chief Research Engineer, focusing on optical design and simulation for optical pick-up units and optical storage devices.
In February 2007, he joined LG Electronics as a Principal Research Engineer and was later promoted to Research Fellow in March 2020. He is currently working on the optical design and analysis of photo-lithographic systems, imaging and illumination systems, and polarization systems.
Abstract
Despite the notable advancements achieved through conventional and cutting-edge strategies, integration technologies utilizing the micro-transfer-printing technique–employing microstructured polymeric stamps, such as polydimethylsiloxane (PDMS) – have garnered considerable attention. This innovative approach facilitates heterogeneous integration by enabling the deterministic placement of micro- and nanoscale optical structures and materials with sub-micrometer alignment onto diverse photonic integration platforms [1–4]. In this talk, we discuss fundamental principles of this integration technology, primarily focusing on the dissipative friction energy during the process, which enables on-demand and high-precision transfer-dragging-assisted micro assembly. The frictional dragging method thus allows for the development of reconfigurable/programmable and heterogeneous nanophotonic integrations, which are the previously challenging and impossible to achieve with conventional strategies.
Biography
You-Shin No received his B.S and Ph.D. degrees in Department of Physics from Korea University, Seoul, Korea, in 2008 and 2014, respectively. He worked as a post-doctoral fellow in the Department of Chemistry and Chemical Biology at Harvard (2014-2017). He became an assistant professor in the Department of Physics at Konkuk University (2017-2021). He became an associate professor in the same department in 2021 (2021-present) and served as a department chair (2022-2024). His research interests include key photonic elements and integrated photonic circuits and systems. In particular, his group focuses on the development of III-V/Si heterogeneous/hybrid and three-dimensional (3D) vertical integration and manipulation technologies, and the development of ultimate light sources at nanoscale (e.g., nanolasers, nanoLEDs, nano-emitters, etc.) and its on-chip, on-demand integration
Abstract
Enabling high-volume manufacturing for EUV lithography has required more than a decade of innovation in patterning materials and processes, from early manufacturability assessments to the introduction of high numerical aperture (high-NA) EUV lithography. Such innovation has been driven not only by ever-shrinking feature dimensions, but also by the need to control stochastic defects, improve pattern transfer, and establish qualification methodologies for new materials introduced into semiconductor manufacturing environments. This presentation reviews recent advances in EUV patterning materials and processes, covering resist screening and benchmarking, qualification of novel materials in a manufacturing-relevant ecosystem, underlayer engineering, electrical tests, and thickness scaling for high-NA EUV lithography. Results from benchmarking of several state of the art resists are used to evaluate the trade-offs between sensitivity, roughness, local CDU, defectivity, and pattern-transfer performance. Particular emphasis is placed on the role of interfaces in EUV patterning performance. Surface energy plays a key role in adhesion of photoresist with underlayer, and this interaction is shown to influence dose, roughness, defectivity, and process windows. Underlayer engineering provides an effective route to tune these interactions, enabling improved lithographic performance beyond what can be achieved through resist optimization alone. Finally, recent progress in MOR integration is reviewed, including benefits associated with enhanced EUV absorption, high etch resistance, and simplified pattern-transfer schemes. Particular attention is given to the high-NA EUV challenges, such as reduced depth of focus, thinner resist layers, line wiggling and metrology.
Biography
Roberto Fallica received his master's degree in Electronics Engineering from Politecnico di Milano (Italy) in 2007 and completed the PhD school in Nanotechnology from University of Milano-Bicocca in 2012 with a thesis on the characterization of phase-change chalcogenide nanowires for nonvolatile data storage. In 2014 he was postdoc researcher at the Paul Scherrer Institute (Switzerland) working at the dedicated EUV/X-ray interference lithography and X-ray absorption spectroscopy beamline for characterization and patterning of nanoscale photoresist structures. Since 2018, he is staff researcher in the Advanced Patterning department of IMEC (Belgium). His duties include the screening of lithography materials and stacks to develop the technology that will enable future semiconductor devices in BEOL (back-end of line) such as DRAM (storage layer) and logic (metalization). In this role, he is focusing on characterization of EUV litho stack materials (photoresist and underlayers) especially for defect mitigation by improving adhesion. In addition, he is in charge of measuring fundamental physical properties of EUV photoresists such as electron blur and electronic processes by photoemission spectroscopy and photocurrent. He is member of SPIE since 2016.
Abstract
Although hybrid tin oxo clusters (SnOCs) hold great promise as high-resolution resists for electron-beam and extreme-ultraviolet lithography, their exact chemical patterning mechanisms remain elusive. Here, we report a ligand-directed synthesis strategy to selectively control cluster nuclearity, yielding distinct Sn6 and Sn3 architectures via electron-donating carboxylate and electron-withdrawing diphenylphosphinate ligands, respectively. DFT calculations and spectroscopic studies (XPS/TOF-SIMS) reveal fundamentally different exposure pathways: Sn6 resists undergo dominant Sn–alkyl cleavage to promote organic–inorganic crosslinking, whereas the robust Sn–O–P core of Sn3 resists suppresses ligand degradation. Consequently, Sn6 resists offer superior sensitivity for sub-30 nm patterning, while Sn3 resists achieve ultra-low line-edge roughness. These insights establish nuclearity control as a key lever for rational molecular-resist engineering.
Biography
Ji-Hyun Jang is a professor of the school of Energy and Chemical Engineering at UNIST in Korea. She received Ph.D. degree in chemistry from KAIST in 2004. After then, she was with Ned Thomas at MSE, MIT as a postdoctoral associate, working on the fabrication of 3D nanostructure via interference lithography. Since she joined UNIST as a faculty, her research has been focusing on new nanomaterials and understanding their functions in energy processes, including photocatalysis for hydrogen generation and electrochemistry for energy-storage devices. Currently, She is also deeply involved in synthesizing and developing physicochemical properties of the 2D materials. Currently, she serves as the director of the Key Research Center for Digital Twin and AI-based Carbon Neutrality at UNIST. She is an Associate Editor of of Materials Today Energy (Elsevier) and editorial board member of ACS Energy Letters (ACS) and Materials Today Catalysis (Elsevier).
Abstract
In this study, CNU-TOC-01(4C-C), a tin oxide cluster photoresist for extreme ultraviolet (EUV) lithography, and dibenzyltin diacetate, an organotin compound, were investigated. The chemical structure of CNU-TOC-01(4C-C) was determined using field desorption time of flight mass spectrometry and small angle X-ray scattering, while impurities present in the resist were identified using nuclear magnetic resonance spectroscopy. To evaluate the chemical contrast and fine-patterning capability of CNU-TOC-01(4C-C), electron-beam lithography was performed at acceleration voltages of 5 and 100 kV. Subsequently, line and space patterns with an 18 nm half pitch were fabricated using EUV lithography. The physical properties of the photoresist were also investigated by evaluating its absorption coefficient and etch resistance. In addition, changes in the photoresist as a function of electron-beam dose were examined using X-ray photoelectron spectroscopy. To investigate the reaction mechanism of tin oxide based photoresists, dibenzyltin diacetate was prepared and employed as a model organotin compound. Dose-dependent changes induced by electron beam irradiation were analyzed using time of flight secondary ion mass spectrometry, Fourier transform infrared spectroscopy, X-ray photoelectron spectroscopy, and Raman spectroscopy. These analyses revealed the decarboxylation reaction of the carboxylate group, which had previously been regarded as an unreactive spacer. To calculate the relative dissociation rates of the Sn–O and O–(C=O) bonds along the dissociation pathways, dimethyltin diacetate and benzylmethyltin diformate were selected as simplified model molecules. The calculations demonstrated that dissociation can proceed through both pathways.
Biography
Abstract
This study presents the design and synthesis of photoresist materials for information display and integrated circuit (IC) applications, the elucidation of solubility-switching mechanisms under photon and electron-beam irradiation, and patterning strategies for their effective implementation. Specifically, chemically orthogonal photoresist materials and processes were investigated for OLED pixel fabrication, in which the processing solvents were chosen to be chemically incompatible with organic semiconductors, thereby preventing damage to the underlying organic layers. Furthermore, imaging mechanisms based on radiation-induced radical chemistry and Lewis acid-base interactions were proposed and experimentally validated for electron-beam and extreme ultraviolet (EUV) lithography using non-chemically amplified photoresists. In addition, chemically orthogonal photoresist systems with distinct imaging characteristics were integrated to demonstrate a multilayer patterning strategy for semiconductor manufacturing. Collectively, these studies provide insights into molecular design, imaging mechanisms, and process strategies for high-resolution lithography and are expected to contribute to advances in next-generation photoresist materials.
Biography
Mar. 2021 –Aug. 2026: Ph.D. in Program in Environment and Polymer Engineering, Inha University, Republic of Korea
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